1. Field of the Invention
The invention relates generally to thermal processing. More particularly, the invention is directed to an apparatus and method for thermally processing a semiconductor substrate by scanning the substrate with a line of radiation.
2. Description of Related Art
The integrated circuit (IC) market is continually demanding greater memory capacity, faster switching speeds, and smaller feature sizes. One of the major steps the industry has taken to address these demands is to change from batch processing silicon wafers in large furnaces to single wafer processing in a small chamber.
During such single wafer processing the wafer is typically heated to high temperatures so that various chemical and physical reactions can take place in multiple IC devices defined in the wafer. Of particular interest, favorable electrical performance of the IC devices requires implanted regions to be annealed. Annealing recreates a more crystalline structure from regions of the wafer that were previously made amorphous, and activates dopants by incorporating their atoms into the crystalline lattice of the wafer. Thermal processes, such as annealing, require providing a relatively large amount of thermal energy to the wafer in a short of amount of time, and thereafter rapidly cooling the wafer to terminate the thermal process. Examples of thermal processes currently in use include Rapid Thermal Processing (RTP) and impulse (spike) annealing. While such processes are widely used, current technology is not ideal. It tends to ramp the temperature of the wafer too slowly and expose the wafer to elevated temperatures for too long. These problems become more severe with increasing wafer sizes, increasing switching speeds, and/or decreasing feature sizes.
In general, these thermal processes heat the wafers under controlled conditions according to a predetermined thermal recipe. These thermal recipes fundamentally consist of: a temperature that the semiconductor wafer must be heated to; the rate of change of temperature, i.e., the temperature ramp-up and ramp-down rates; and the time that the thermal processing system remains at a particular temperature. For example, thermal recipes may require the wafer to be heated from room temperature to distinct temperatures of 1200° C. or more, for processing times at each distinct temperature ranging up to 60 seconds, or more.
Moreover, to meet certain objectives, such as minimal diffusion, the amount of time that each semiconductor wafer is subjected to high temperatures must be restricted. To accomplish this, the temperature ramp rates, both up and down, are preferably high. In other words, it is desireable to be able to adjust the temperature of the wafer from a low to a high temperature, or visa versa, in as short a time as possible.
The requirement for high temperature ramp rates led to the development of Rapid Thermal Processing (RTP), where typical temperature ramp-up rates range from 200 to 400° C./s, as compared to 5-15° C./minute for conventional furnaces. Typical ramp-down rates are in the range of 80-150° C./s.
FIG. 1 is a graph 100 of thermal profiles of different prior art thermal processes. As can be seen, the thermal profile 102 of a typical RTP system has a 250° C./s ramp-up rate and a 90° C./s ramp-down rate.
A drawback of RTP is that it heats the entire wafer even though the IC devices reside only in the top few microns of the silicon wafer. This limits how fast one can heat up and cool down the wafer. Moreover, once the entire wafer is at an elevated temperature, heat can only dissipate into the surrounding space or structures. As a result, today's state of the art RTP systems struggle to achieve a 400° C./s ramp-up rate and a 150° C./s ramp-down rate.
FIG. 1 also shows a thermal profile 104 of a laser annealing process. Laser annealing is used during the fabrication of thin film transistor (TFT) panels. Such systems use a laser spot to melt and recrystalize polysilicon. The entire TFT panel is exposed by scanning the laser spot across successive exposure fields on the panel. For wafer applications a laser pulse is used to illuminate an exposure field for a duration of approximately 20-40 ns, where the exposure field is typically about 25 by 35 mm. As can be seen from the thermal profile 104 for laser annealing, the ramp rate is nearly instantaneous at billions of degrees per second. However, the laser pulse or flash used for laser annealing is too fast and, often does not provide enough time for sufficient annealing to occur for non-melt processes. Also, devices or structures next to the exposed regions may be exposed to extreme temperatures causing them to melt, or to temperatures that are too low resulting in too little annealing. Still further, homogenization of the thermal exposure of each portion of the wafer is difficult to attain because different regions adsorb at different rates resulting in huge temperature gradients. The process is too fast for thermal diffusion to equilibrate temperature, thereby creating severe pattern dependencies. As a result, this technology is not appropriate for single crystal silicon annealing because different regions on the wafer surface may be heated to vastly different temperatures causing large non-uniformities over short distances.
Another thermal processing system currently in development by Vortek Industries Ltd., of Canada, uses flash assisted spike annealing to attempt to provide a high thermal energy to the wafer in a short of amount of time and then rapidly cool the region to limit the thermal exposure. Use of this thermal processing system should give the junction depth of a spike anneal to 1060° C. but improve the activation with flash to 1100° C. Typically, the RTP system ramps up to the desired temperature typically around 1060° C. then begins to ramp down immediately after having reached the desired flash temperature. This is done to minimize the amount of diffusion that takes place while still getting suitable activation from the elevated temperature. The thermal profile 106 of such a flash assisted spike anneal is also shown in FIG. 1.
In view of the above, there is a need for an apparatus and method for annealing a semiconductor substrate with high ramp-up and ramp-down rates. This will offer greater control over the fabrication of smaller devices leading to increased performance. Furthermore, such an apparatus and method should ensure that every point of the wafer has a substantially homogenous thermal exposure, thereby reducing pattern dependencies and potential defects.